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3.1 megapixel cmos senso r CYIWOSC3000AA cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-19009 rev. *e revised april 03, 2006 features ? hisens? high sensitivity in low-light conditions ? 1/2.8? optical format image sensor ? fast frame readout at full resolution ? progressive scan ?i 2 c serial control interface ? selectable 8 and 12 bit parallel data port ? low-power 30 frames/s preview mode ? programmable controls: frame size, frame rate, gain exposure, blanking, flip a nd mirroring, windowing, auto black level offset correction and panning ? horizontal and vertical binning for increased sensitivity ? available in 48-pin plcc package applications ? cellular phone camera modules ? pocket pcs ?pdas ?toys ? battery operated devices table 0-1. key performance parameters parameter typical value optical format 1/2.8-inch active imager size 5.2 mm x 3.9 mm active pixels 2048h x 1536v pixel size 2.54 m x 2.54 m color filter array r gb bayer pattern shutter type electronic rolling shutter maximum data rate/ master clock 48 mps/48 mhz frame rate 14 fps (2048 x 1536) 80 fps (640 x 480) adc resolution 12-bit (72 db), on-chip dynamic range 55 db responsivity >1.0v/lux-sec (550 nm) snr max in db qxga: 35 vga: 40 supply voltage @ 25c analog: 2.5v?3.1v digital: 1.65v?2.0v i/o: 1.8v?2.8v analog and digital power consumption 60 mw @ 30 fps (640 x 480) 215 mw @ 15 fps (2048 x 1536) operating temperature ?30c to +70c packaging 48-pin plcc
cyiwosc3000a a document #: 38-19009 rev. *e page 2 of 37 table of contents features ...................................................................................................................... ....................................... 1 applications .................................................................................................................. ................................... 1 1.0 general description ....................................................................................................... ........................ 4 2.0 pin description ........................................................................................................... ............................... 5 3.0 functional overview ....................................................................................................... ....................... 6 4.0 signal description ........................................................................................................ ........................... 7 5.0 pixel array structure ..................................................................................................... ...................... 8 6.0 data formats .............................................................................................................. ............................... 9 6.1 frame timing .............................................................................................................. .................................................. 9 6.2 frames per second and integratio n time calculation ........................................................................ ........................ 10 6.3 output data timing .................................. ...................................................................... ............................................. 10 7.0 serial bus description .................................................................................................... ..................... 11 7.1 serial bus protocol ....................................................................................................... ............................................... 11 7.2 detailed timing ........................................................................................................... ................................................. 11 7.3 single random write ....................................................................................................... ......................................... 12 7.4 multiple write ............................................................................................................ ................................................ 12 7.5 single random read ........................................................................................................ ......................................... 12 7.6 multiple sequential read ..... .............. .............. .............. .............. .............. .............. ......... ......................................... 12 8.0 registers ................................................................................................................. .................................. 13 8.1 register map .............................................................................................................. ................................................. 13 8.2 control registers ......................................................................................................... ................................................ 15 8.3 status registers .......................................................................................................... ................................................ 30 9.0 feature descriptions ...................................................................................................... ..................... 32 9.1 hisens? ................................................................................................................... ................................................. 32 9.2 power saver settings .................................. .................................................................... ............................................ 32 9.3 selectable frame rate ..................................................................................................... ........................................... 32 9.4 fpn reduction ............................................................................................................. ............................................... 33 9.5 black level setting and averaging .................... ..................................................................... ..................................... 33 9.6 digital gain per color ......... ........................................................................................... .............................................. 33 9.7 exposure control .......................................................................................................... ............................................... 33 9.8 resolution control ....................................... ................................................................. ............................................... 33 9.9 sub-window control ........................................................................................................ ............................................ 33 9.10 analog on-chip binning ................................................................................................... .......................................... 33 9.11 digital on-chip binning .................................................................................................. ............................................ 33 9.12 50-/60-hz flicker reduction ......................... ..................................................................... ........................................ 33 9.13 blanking time, pclk and sync po larity .................................................................................... ................................ 33 9.14 power-on reset ........................................................................................................... .............................................. 34 9.15 on-chip test pattern generation .......................................................................................... ..................................... 34 9.16 exposure control region of interest (roi) ................................................................................ ................................ 34 9.17 register setting sync contro l ............................................................................................ ........................................ 34 9.18 preview and video mode ................................................................................................... ........................................ 34 9.19 parallel digital interface .......................... ..................................................................... .............................................. 34 10.0 electrical specifi cations ....... ................ ................ ................. ................ ............. ........... ................ 35 10.1 absolute maximum ratings ............................. .................................................................... ...................................... 35 10.2 operating conditions ..................................................................................................... ............................................ 35 11.0 electrical characteristics ...................... ......................................................................... ............. 35 12.0 48-pin plcc package diagram .............................................................................................. ............. 36 12.1 ordering information ............ ......................................................................................... ............................................. 36
cyiwosc3000a a document #: 38-19009 rev. *e page 3 of 37 list of figures figure 1-1. block diagram ...................................................................................................... ................................. 4 figure 2-1. bond diagram for 48 -plcc package................................................................................... ................. 5 figure 3-1. typical configuration .................. ............................................................................ ............................... 6 figure 5-1. pixel array ........................................................................................................ ..................................... 8 figure 6-1. frame timing ................................ ....................................................................... ................................. 9 figure 6-2. row timing......................................................................................................... ................................. 10 figure 6-3. row timing with binning .............. .............................................................................. ........................ 10 figure 6-4. pixel data timing .......................... ........................................................................ .............................. 11 figure 7-2. single random write................................................................................................ ........................... 11 figure 7-1. serial bus timing .................................................................................................. .............................. 11 figure 7-3. multiple write ..................................................................................................... .................................. 12 figure 7-4. single random read ................................................................................................. ......................... 12 figure 7-5. multiple sequential read............... ............................................................................ .......................... 12 figure 9-1. smpte color bars ................................................................................................... ........................... 34 figure 12-1. 48-pin plcc packa ge diagram ....................................................................................... ................. 36 list of tables table 0-1. key performance parameters .............. ........................................................................... ...................... 1 table 4-1. signal description ................................................................................................. ................................. 7 table 6-1. embedded sync ...................................................................................................... .............................. 9 table 8-1. register map ....................................................................................................... ................................ 13 table 9-1. power modes ....... ................................................................................................. ............................... 32 table 9-2. typical power consumpti on in common operating modes ................................................................ 32 table 11-1. environmental specifications ...................................................................................... ....................... 35 table 12-1. ordering info rmation .............................................................................................. ............................ 36
cyiwosc3000a a document #: 38-19009 rev. *e page 4 of 37 1.0 general description cypress semiconductor corporation?s (cypress?s) cmos sensor is a 3.1-megapixel (qxga) format, 1/2.8-inch active-pixel digital image sensor with an active imaging pixel array of 2048h x 1536v. the sensor incorporates camera functions such as frame size/rate, flip, mirroring and binning for increased sensitivity. the se nsor functions are all program- mable through a i 2 c serial interface. the megapixel cmos sensor features cypress?s hisens circuitry, which dramatically improves low light sensitivity without increasing the number of transistors used in the pixel and maintains the fill factor while reducing the cost and complexity of the sensor. an on-chip analog-to-digital converter (adc) provides 12 bits per pixel. the sensor can be programmed by the user to meet the application specific requireme nts such as windowing, gain, panning and other parameters. the sensor can output a qxga image up to 14 frames per second (fps). figure 1-1. block diagram pixel-array 2080 x 1568 adc data out 8/12-bit readout sequencer i 2 c serial control 2.8v analog reset clk 1.8v digital image processing camera control processor hsync pixclk vsync pixel-array 2080 x 1568 adc data out 8/12-bit readout sequencer i 2 c serial control 2.8v analog reset clk 1.8v digital image processing camera control processor hsync pixclk vsync
cyiwosc3000a a document #: 38-19009 rev. *e page 5 of 37 2.0 pin description note: the sensor die is placed in the package so that the ar ray center (optical center) of the die is centered in the package. the die is offset in the ?y? direction by 1.119 mm to achieve this. figure 2-1. bond diagram for 48-plcc package
cyiwosc3000a a document #: 38-19009 rev. *e page 6 of 37 3.0 functional overview the sensor is a progressive- scan sensor that generates a stream of pixel data qualified by hsync and vsync signals. in default mode, the data rate (pixel clock) is the same as the master clock frequency, one pixel is generated every master clock cycle. the core of the sensor is an active-pixel array. the timing and control circuitry sequences th rough the rows of the array, resetting and then reading each row. in the time interval between resetting and reading a row, the pixels in that row integrate incident light. the exposure is controlled by varying the time interval between reset and readout. after a row is read, the data from the columns is sequenced through an analog signal chain (providing offset correction), and then through an adc. the output from the adc is a 12-bit value for each pixel in the array. the pixel array contains optically active and light-shielded ?black? pixels. the black pixels are used to provide data for on-chip offset correction algorithms (black level control). the sensor contains a set of 8- bit control and status registers that can be used to control ma ny aspects of the sensor opera- tions. these registers can be accessed through a i 2 c serial interface. in this document, re gisters are specified either by name (e.g., column start) or by register address (e.g., reg0x04). fields within a register are specified by bit or by bit range (e.g., reg0x20[0] or re g0x0b[13:0]. the control and status registers are described in registers, section 8.0. the output from the sensor is a bayer pattern: alternate rows are a sequence of eit her green/red pixels or blue/green pixels. the offset and gain stages of the analog signal chain provide per-color control of the pixel data. figure 3-1 shows a typical module wiring diagram. vddio can be connected to either the 1.8v supply or the 2.8v supply (but not both) to match the voltage requirements of the back-end processing chip. it is recommended that the 1.8v supply be used to minimize power consumption. the capacitor for the vddio supply is optional but the capacitors for vddd and vdda are required and must provide sufficient decoupling on the module to insure clean supply voltages. note that anlg[2:0] must be connected to capacitors to minimize image noise. anlg[3] is only for test purposes and should be unconnected. note that reset_n is typically connected with an rc circuit to hold reset_n low until both power supplies have reached their proper level. clk reset_n sclk sdat sbia3 test tck tms pixclk d[11:0] hsync vsync tdo tdi anlg3 anlg2 anlg1 anlg0 vdda gnda gnda vddio gndio vddd gndd 2.8v 1.8v gnd sdat sclk reset_n clk pixclk d[11:0] hsync vsync vddio 1f 100k 1f 1f 1f 1f 1f 1f clk reset_n sclk sdat sbia3 test tck tms pixclk d[11:0] hsync vsync tdo tdi anlg3 anlg2 anlg1 anlg0 vdda gnda gnda vddio gndio vddd gndd 2.8v 1.8v gnd sdat sclk reset_n clk pixclk d[11:0] hsync vsync vddio 1f 100k 1f 1f 1f 1f 1f 1f figure 3-1. typical configuration
cyiwosc3000a a document #: 38-19009 rev. *e page 7 of 37 4.0 signal description table 4-1. signal description pin function type note 1 vddd power digital core power (1.8v nominal) 2 pixclk output pixel clock (data strobe) 3 d6 output digital video out 4 d7 output digital video out 5 d8 output digital video out 6 d9 output digital video out 7 d10 output digital video out 8 d11 output digital video out (msb) 9 vddio bidirectional digital io supply (1.8v nominal or 2.8v) 10 gndio power io ground 11 vdda power analog supply to pixel array (2.8v nominal) 12 gnda power analog ground 13 anlg[0] bidirectional analog debug 14 anlg[1] bidirectional analog debug 15 test input test mode 16 sbia3 input serial bus interface address bit 3 17 tdi input jtag data in 18 anlg[2] bidirectional analog debug 19 anlg[3] bidirectional analog debug 20 reset_n input reset active low 21 gndd power digital ground 22 clk input input clock (up to 48 mhz) 23 d0 output digital video out 24 d1 output digital video out 25 d2 output digital video out 26 d3 output digital video out 27 d4 output digital video out 28 d5 output digital video out 29 vddio bidirectional digital io supply (1.8v nominal or 2.8v) 30 gndio bidirectional io ground 31 vdda bidirectional analog supply to pixel array (2.8v nominal) 32 gnda power analog ground 33 tck input jtag clock 34 tms input jtag 35 vsync output frame sync 36 hsync output line sync 37 tdo output jtag data out 38 gpio bidirectional general purpose digital io 39 sclk input i 2 c serial communications clock 40 sdat bidirectional i 2 c serial communications data
cyiwosc3000a a document #: 38-19009 rev. *e page 8 of 37 5.0 pixel array structure the sensor device is a camera on a chip cmos imager with 3-megapixel resolution (qxga) in a 1/2.8? optical format. this requires a 2.54- m square pixel pitch for adequate sensitivity. figure 5-1 below shows the layout of the pixel array. the 12 outermost rows and columns of the array are covered with metal and are thus optically black. the black rows can also be set via internal registers to be read out as valid frame data. there are 2048h x 1536v optically active pixels surrounded by an additional 2 bayer patterns (4 pixels) around the image to avoid boundary effects during color interpolation and correction. the sensor is designed with a mo saic of color filters arranged in a standard bayer pattern shown in figure 5-1 . the odd numbered columns contain green and blue pixels as do the odd numbered rows. correspondingly, the even rows and even columns contain green and red pixels. the imager will output either all bayer patterned pixels or all physical pixels based upon register settings. the bayer primitive pattern at the periphery should be used for border interpolation. col 2079 col 2068 col 2066 col 2063 col 13 col 11 row 0 row 11 row 13 row 16 col 0 row 1554 row 1556 row 1567 2048h x 1536v 12 rows 12rows 2080h x 1568v total pixels ( 2056h x 1544v active pixels) 12 columns 12 columns col 16 g r g b row 1551 column readout direction row readout direction g r g b g r g b g r g b g r g b g r g b g r g b g r g b r g r g g r g b g r g b g r g b g r g b g r g b g r g b g r g b g r g b r g r g g r g b g b g r g b g r g b g r g b g b g r g b g r g b r g r g g r g b g b g r g b g r g b g r g b g b g r g b g r g b r g r g g b g b g b g b g r g b g r g b g r g b g r g b g r g b g r g b g r g b g r g b r g r g g r g b g r g b g r g b g r g b g r g b g r g b g r g b g r g b r g r g g r g b g b g r g b g r g b g r g b g b g r g b g r g b r g r g g r g b g b g r g b g r g b g r g b g b g r g b g r g b r g r g g b g b g b g b col 2079 col 2068 col 2066 col 2063 col 13 col 11 row 0 row 11 row 13 row 16 col 0 row 1554 row 1556 row 1567 2048h x 1536v 12 rows 12rows 2080h x 1568v total pixels ( 2056h x 1544v active pixels) 12 columns 12 columns col 16 g r g b row 1551 column readout direction row readout direction g r g b g r g b g r g b g r g b g r g b g r g b g r g b r g r g g r g b g r g b g r g b g r g b g r g b g r g b g r g b g r g b r g r g g r g b g b g r g b g r g b g r g b g b g r g b g r g b r g r g g r g b g b g r g b g r g b g r g b g b g r g b g r g b r g r g g b g b g b g b g r g b g r g b g r g b g r g b g r g b g r g b g r g b g r g b r g r g g r g b g r g b g r g b g r g b g r g b g r g b g r g b g r g b r g r g g r g b g b g r g b g r g b g r g b g b g r g b g r g b r g r g g r g b g b g r g b g r g b g r g b g b g r g b g r g b r g r g g b g b g b g b figure 5-1. pixel array
cyiwosc3000a a document #: 38-19009 rev. *e page 9 of 37 6.0 data formats the imager is read out in a progressive scan fashion. this means that each successive row is read out in an increasing row number. the data is digitized via on chip a/d converters and the output resolution is selectable at 8 and 12 bits resolution. the pixel data is output in parallel with synchroni- zation signals for frame (vsyn c), line (hsync), and pixel (pixclk). the frame and line sync signals may be embedded in the data as set by internal registers. when sync signals are embedded in the data, the numbers of available colors is reduced by one value. the embedded sync values are indicated by a pattern of 0xff, 0x00, 0x00, sync_value where sync_value is listed in table 6-1 . to prevent sync from being inadvertently indicated in the active portion of the image, the 0xff value is remapped to 0xfe when operating in 8-bits/pixel mode. the embedded sync format follows several industry standards including itu-r bt.656. with discrete sync signals, th e polarity of the hsync, vsync, and pixclk may be independently inverted with respect to the active pixel readout. hsyn c and vsync toggle even when embedded syncs are enabled. the resolution is set by three factors. the resolution may be decreased by sub-windowing a smaller region of interest (roi), as set in the internal registers. the imager can also be programmed to sub-sample the array to read out every n th bayer rows and m th bayer columns. finally, the imager can be programmed to bin (combine) adjacent pixels of similar color in both row and column directions independently with strengths of 2, 3, or 4. the output data can be shifted down by 4 bits to accommodate back-end processors that want to switch from processing 12-bit data to 8-bit data where the lsbs must remain at bit zero on the pixel bus. 6.1 frame timing a frame of data is comprised of valid image data which is output when the hsync and vsync signals are inactive (1). frame rate is computed as a function of the clk frequency, the row timing, the number of ro ws and the number of vertical blanking (vblank) rows programmed. the frame timing is programmable via a number of registers described later in this document. interfacing to a back-end processor involves the control signals, hsync and vsync, and the appropriate pixclk timing. the imager has several programmable modes to allow interfacing to a wide variety of back-end processors. figure 6-2 shows typical in terface signals. there are two basic modes of operation, hsync and datval. in hsync mode, the hsync signal indicates the start of a new row of the image. in this mode pixclk only clocks when there is valid data on the pixdata bus. in datval mode, pixclk runs throughout the hblanking period (or optionally free-runs) and the hsync signals becomes a data valid signal which tells the back-end processor when there is valid data on the pixdata bus. note that if dark pixels are enabled to be output or if digital horizontal binning is used, datval will toggle many times during a single row. enabling embedded syncs does not change the row or frame timing. the 4-byte sync fields are inserted into the data stream during the hblank time (hblank must be at least 8). the timing diagram in figure 6-2 shows the detailed row timing of all of the modes that the imager can produce. the hsync signal can be programmed to be either hsync or datval. pixclk can be progr ammed in four different operating modes. depending on the back-end processor, some modes will work better than others. generally datval mode with pixcldk mode = 10 is the most common mode. in this mode the hsync signal is acting as a data valid pulse. pixclk runs continuously except when invalid data is on the pixdata bus. in the diagram above, clk 4 is when the dark pixels are being processed. if the dark pixels were enabled to be output then clk 4 would be high. note that the number of clocks is significantly reduced in this diagram for ease of viewing. hsync is typically lo w for 16 or more clocks and there are 24 dark pixels, not just the one shown here. the row timing gets more complicated when horizontal binning or subsampling is enabled (see figure 6-3 ). the timing diagram shows the case where hbin by 2 is enabled. note that since the output format is bayer patterns, it outputs 2 pixels, then skip (or bin) 2 pixels. note that when using datval mode, the datval signal will toggle many times each row. however, using pixclk mode = 01, the backend processor will not clock in the pixels when datval is low and thus it looks to the processor like datval is always high when there is valid data. table 6-1. embedded sync sync_value description 00 row start 01 row end 02 frame start 03 frame end vblank region dark pixels hblank region hsync datval vsync datval active pixels programmed active region vblank region dark pixels hblank region hsync datval vsync datval active pixels programmed active region figure 6-1. frame timing
cyiwosc3000a a document #: 38-19009 rev. *e page 10 of 37 pixclk mode = 11 is typically only used in datval mode. otherwise, the processor has to clock in every pixel in a frame and then compute which ones are valid and which ones re not based on the bin/subsampling modes. 6.2 frames per second and integration time calculation the number of frames per second taken by the osprey is programmable. it can vary from le ss then 1 fps to 14 fps in full resolution capture mode (and can be much higher in reduced resolution modes). the frame rate is dictated by input clk frequency, the total number of rows output per frame and the time required to read out a single row. the total number of rows output and the time required to output a row can be calculated using simple formula?s based on i 2 c register reads. rownum register (0x4) stores the number of active rows output.colcnt register (0xa8) stores the # of clks required to read out a single row (hence time required to read out a single row is colcnt / clk freq. colcnt is modified based on active number of columns output (colnum register (0x6) and the hblank register (0x8,0x9), which adds additional clk cycles onto the end of the row readout). note that colcnt is a 12bit register. frames/second = clock frequency / (total number of rows per frame * colcnt (register 0xa8 and 0xa9)) where total number of rows per frame =rownum(register 0x4 and 0x5 +1)+ vblank(0xc and 0xd) + number of dark rows. the rownum register will have a value 1 less than actual number of active rows and hence an addition of 1 in the formula. the dark rows are the optically black rows located towards the periphery to calculate the black level. at least 4 rows must be turned on to properly compute the dark current. by default, the middle 4 rows are turned on which typically are the best for computing dark current. pl ease refer section 7.2.36. integration time calculation tint (in seconds) = colcnt (register 0xa8 and 0xa9) * inttime (register 0xe and 0xf) / clock frequency it is recommended that inttime should not be set larger than the total number of rows per frame. 6.3 output data timing the pixel output bus has programmable polarities for the clock and the sync signals to simplify timing to the back-end processor. the timing of all of the signals is relative to pixclk. the delay time for hsync, vsync and the pixdat bus to be valid relative to the selected edge of pixclk is a minimum of 0 ns (ddsmin) and a maximum of 4 ns (tdsmax). figure 6-2. row timing hsync datval pixdata mod=00 mod=01 0 mod=10 mod=11 ? 1 2 3 2045 2046 2047 2047 ? 2043 ? pixclk 0 12345678910111213141516 hsync datval pixdata mod=00 mod=01 0 mod=10 mod=11 ? 1 2 3 2045 2046 2047 2047 ? 2043 ? pixclk hsync datval pixdata mod=00 mod=01 0 0 mod=10 mod=11 ? ? 1 1 2 2 3 3 2045 2045 2046 2046 2047 2047 2047 2047 ? ? 2043 2043 ? ? pixclk 0 12345678910111213141516 figure 6-3. row timing with binning hsync datval pixdata mod=00 mod=01 0 mod=10 mod=11 4 1 2 3 2045 2046 2047 2047 ? 2043 ? pixclk 5 6 ? 0 1234567891011121314151617 18 19 hsync datval pixdata mod=00 mod=01 0 mod=10 mod=11 4 1 2 3 2045 2046 2047 2047 ? 2043 ? pixclk 5 6 ? hsync datval pixdata mod=00 mod=01 0 0 mod=10 mod=11 4 4 1 1 2 2 3 3 2045 2045 2046 2046 2047 2047 2047 2047 ? ? 2043 2043 ? ? pixclk 5 5 6 6 ? ? 0 1234567891011121314151617 18 19
cyiwosc3000a a document #: 38-19009 rev. *e page 11 of 37 figure 6-4. pixel data timing 7.0 serial bus description the CYIWOSC3000AA includes a serial control interface that allows the application processor to control the imager using only two signals. the serial bus interface (sbi) is a simple bidirectional communication interface based on the i 2 c protocol that is in wide use throughout the industry. the serial bus operates at speeds of up to 400,000 bits per second. the interface is a multi-drop protocol which allows multiple devices to be connected to a single pair of wires and can be used between numerous standard image processing chips. the two interface signals are called sclk and sdat. sclk provides a clock for asserting and sampling the sdat signal. sclk is unidirectional from the bus master, typically an image processing chip, to the CYIWOSC3000AA image sensor. sdat is the data bus and is bidirectional. both signals are open-drain and require a pull- up resistor of 1.5k ohms. data is always transmitted with the most-significant-bit (msb) first. eight bits of data are always transferred and are followed by a single acknowledge bit. 7.1 serial bus protocol data transfer on the serial bus interface is initiated with a start condition. the start condition is indicated when the sdat signal goes low while sclk remains high. the start condition may be initiated at anytime during a transfer and the imager will restart the transfer to begin accepting the slave address which must immediately follow the start. the sdat line must only transition when sclk is low when data is being transferred. if sdat transitions while sclk is high, then it will be interpreted as either a start or a stop condition. sufficient timing margins must be provided around the rising and falling edges of sclk to insure that a start or stop condition are not mistakenly recognized. the slave address is a sequence of 7 bits, a read/write bit and an acknowledge bit. data is always transmitted msb first and lsb last as shown in figure 7-1 . the slave address is 7 bits long and must be 1110_x10 (0xe4 or 0xec) where x is the state of the sbia3 pin. the sbia3 pin allows two CYIWOSC3000AA image sensors to be connected to the same serial bus interface. the lsb of the slave address is the read/write bit where a high (1) indicates that a read cycle will follow and a low (0) indicates that a write cycle will follow. after the read/write bit, the CYIWOSC3000AA image sensor will assert sdat low shortly after sclk goes low to acknowledge that the slave address has been recognized and is ready to process the command that will follow. if a read transaction has been requested (read/write is high), then the imager will begin driving sdat with the register data at the current address. if a write transaction has been requested then the bus master should send the two reg address bytes. the reg address bytes specifies which register in the imager is to be accessed. the next byte of data is the writ e data. additional bytes of data can be written and the address will be automat ically incre- mented to the next register. upon completion of all data being transferred, the master should issue a stop command to place the sbi in an idle state. a stop command is initiated by first driving sdat low and sclk high, then bringing sdat high while sclk remains high. 7.2 detailed timing figure 7-1 shows the detailed timing of each byte of data to be transferred on the sbi. a transfer begins with the start condition. this is always followed by 8-bits of data. the acknowledge bit always follows the data which is from the receiver of the data to the transmitter. additional bytes of data can then be transferred until either the stop condition or another start condition is detec ted. data is always trans- ferred most-signifi cant-bit first. tdsmin tdsmax pixclk tdsmin tdsmax pixclk figure 7-2. single random write s slave addr 0 addr msb a a data a p single random write s p a start stop acknowledge from slave addr lsb a s slave addr 0 addr msb a a data a p single random write s p a start stop acknowledge from slave addr lsb a figure 7-1. serial bus timing sclk sdat 7 6 5 4 3 2 1 0 a start stop a ck 7 6 5 4 3 2 1 0 a start stop a ck
cyiwosc3000a a document #: 38-19009 rev. *e page 12 of 37 7.3 single random write a write cycle to any register is accomplished by sending a start followed by a 7 bit slave address, one bit of zero (the read/write indicator) and an ack bit (see figure 7-2 ). then the 16-bit register address must be sent in two bytes, each with an ack bit from the slave. finally the 8-bits of data are sent and the slave will res pond with a final ack bit. the master can then either issue a stop command or write to the next sequential address by sending additional data bytes. 7.4 multiple write multiple registers can be written in a single stream of data which reduces the time required to update registers. in figure 7-3 , data would be written to the address given in addr. data+1 would be written to addr+1 and so on with each byte of data being written to the next higher register address. 7.5 single random read a single random read cycle requires that a dummy write cycle be done first so that the register address can be set. the first slave addr is followed with a 0 bit which indicates that this is a write cycle. the register address follows but instead of sending the data to write, a new start condition is sent which restarts the sbi state machine but the reg addr remains initialized. the slave addr must be sent again but this time is followed with a 1 bit indicating that this is a read cycle. the slave responds with the ack bit and then drives the 8 data bits of the register which has been read. after the eight data bits, the slave does not assert the ack bit. instead, it tri-states the sdat signal so that the master can either ack, or assert the stop condition. 7.6 multiple sequential read multiple sequential registers can be read without having to resend the slave addr and register addresses. to read multiple registers, simply continue to issue more sclks and the imager will increment to th e next higher register address. after each byte that is transferred, the master must issue an ack by driving sdat low if it wishes to continue to read more data. the last byte that is read should not ack, which allows the master to drive sdat low before releasing sclk and then release sdat to cause a stop condition to be recognized. alternatively, if the master does not drive sdat low during the ack bit, the imager will release the sdat line and the state machine will return to its idle state waiting for the next start condition. the register addr is always retained at the current address as long as power is applied to the chip. a register read at the current address can be initiated at any time without having to send the register addr first if the desired register is already being addressed. note that the register address is incre- mented on the rising edge of sclk at the start of the ack bit. figure 7-3. multiple write s slave addr 0 addr lsb a a data a p multiple sequential write s p a start stop acknowledge from slave data +1 a ? data +n a addr msb a s slave addr 0 addr lsb a a data a p multiple sequential write s p a start stop acknowledge from slave data +1 a ? data +n a addr msb a figure 7-4. single random read a s p a start stop acknowledge from slave acknowledge from master a p p s p a start stop acknowledge from slave acknowledge from master s slave addr 0 addr lsb a a data s slave addr 1 a addr msb a s slave addr 0 addr lsb a a data s slave addr 1 a addr msb a a s p a start stop acknowledge from slave acknowledge from master a p p p p s p a start stop acknowledge from slave acknowledge from master s slave addr 0 addr lsb a a data s slave addr 1 a addr msb a s slave addr 0 addr lsb a a data s slave addr 1 a addr msb a s slave addr 0 addr lsb a a data s slave addr 1 a addr msb a s slave addr 0 addr lsb a a data s slave addr 1 a addr msb a ? s slave addr 0 addr lsb a a data a p sequential read s p a start stop acknowledge from slave s slave addr 1 a acknowledge from master a data +1 a data +n addr msb a ? s slave addr 0 addr lsb a a data a p sequential read s p a start stop acknowledge from slave s slave addr 1 a acknowledge from master a data +1 a data +n addr msb a figure 7-5. multiple sequential read
cyiwosc3000a a document #: 38-19009 rev. *e page 13 of 37 8.0 registers 8.1 register map table 8-1. register map addr name 7 6 5 4 3 2 1 0 description 00 rowsh [1] f rowsh row start address high 01 rowsl [1] rowsl row start address low 02 colsh [1] m colsh column start address high 03 colsl [1] colsl column start address low 04 rownumh [1] rownumh number of rows high 05 rownuml [1] rownuml number of rows low 06 colnumh [1] colnumh number of columns high 07 colnuml [1] colnuml number of columns low 08 hblankh hblankh horizontal blanking high 09 hblankl hblankl horizontal blanking low 0a devid devid=0x4f(?o?) device identification 0b version version silicon version 0c vblankh vblankh vertical blanking high 0d vblankl vblankl vertical blanking low 0e inttimeh inttimeh integration time high 0f inttimel inttimel integration time low 10 rgainh [1] rgainh red gain integer 11 rgainl [1] rgainl red gain fraction 12 grgainh [1] grgainh green-red gain integer 13 grgainl [1] grgainl green-red gain fraction 14 gbgainh [1] gbgainh green-blue gain integer 15 gbgainl [1] gbgainl green-blue gain fraction 16 bgainh [1] bgainh blue ga in integer 17 bgainl [1] bgainl blue gain fraction 18 gain e digital gain enable 1e tintinch e tintinc tint increment high 1f tintinvl tintinc tint increment low 20 roixsh [1] roixsh region of interest x start high 21 roixsl [1] roixsl region of interest x start low 22 roiwxh [1] roiwxh region of interest x width high 23 roiwxl [1] roiwxl region of interest x width low 24 roiysh [1] roiysh region of interest y start high 25 roiysl [1] roiysl region of interest y start low 26 roiwyh [1] roiwyh region of interest y width high 27 roiwyl [1] roiwyl region of interest y width low 28 aemaxh aemaxh auto exposure maximum high 29 aemaxl aemaxl auto exposure maximum low note: 1. registers controlled by the sync bit.
cyiwosc3000a a document #: 38-19009 rev. *e page 14 of 37 2a aeminh aeminh auto exposure minimum high 2b aeminl aeminl auto exposure minimum low 2c aeavgh aeavgh auto exposure desired average luminance high 2d aeavgl aeavgl auto exposure desired average luminance low 2f exposure e i d f exposure controls 30 blklvlh [1] blkh black level high 31 blklvll [1] blkl o black level low 32 darkmode e mod dark current subtraction mode 33 fpnmode hm vm fixed pattern noise modes 35 abin abin vbin analog binning 36 hbin s b hb1 w b hb2 horizontal binning 37 vbin s b vbo w b vbin vertical binning 38 pixrepl t e pixel replacement 39 datafmt e f c p 8 d pixel data format (8/12 bits) 3a syncpol v h d p mod vsync, hsync, pixclk polarity 3b tstptn mod test pattern enable 3c flip m f flip/mirror 3e darktoph top dark row enable high 3f darktopl top dark row enable low 60 gpio 61 i 2 cio 62 pclkio 63 pixio 70 pwrctl i h t power and io control 7e reset reset device reset register 7f sync e n v register synchronization status & statistics registers 80 gravgh gravgh green-red average high 81 gravgl gravgl green-red average low 82 gbavgh gbavgh green-blue average high 83 gbavgl gbavgl green-blue average low 84 ravgh ravgh red average high 85 ravgl ravgl red average low 86 bavgh bavgh blue average high 87 bavgl bavgl blue average low 88 lumavgh lumavgh luminance average high 89 lumavgl lumavgl luminance average low table 8-1. register map (continued) addr name 7 6 5 4 3 2 1 0 description
cyiwosc3000a a document #: 38-19009 rev. *e page 15 of 37 8.2 control registers 8.2.1 rowsh(00) & rowsl(01) rowsh and rowsl are a register pair that make up a twelve-bit register. the upper 3 bits of rowsh are reserved. the lower 4 bits of rowsh make up the 4 most significant bits of the starting row and rowsl make up the low eight bits. the starting row address is normally twelve to begin the display with the first ro w of active pixels. when zooming in, the rows registers are us ed to start the image in the sub-window area of the image. 8.2.2 colsh(02) & colsl(03) colsh and colsl are a register pair that make up a twelve-bit register. the upper 3 bits of colsh are reserved. the lower 4 bits of colsh make up the 4 most significant bits of the starting column and colsl make up the low eight bits. the starting column address is normally twelve to begin the display with the first column of active pixels. when zooming in, the cols regist ers are used to start the image in the sub-window area of the image. 8.2.3 rownumh(04) & rownuml(05) a0 replpix replpix number of pixels replaced a1 currow currow current row being output (8 msbs only) a2 noisevarh noisevarh dark noise variance high a3 noisevarl noisevarl dark noise variance low a4 actrowsh actrowsh number of active rows high a5 actrowsl actrowsl number of active rows low a6 actcolsh actcolsh number of active columns high a7 actcolsl actcolsl number of active columns low a8 colcnth colcnt column count high a9 colcntl colcnt column count low aa tintaeh tintaeh autoexposure tint high ab tintael tintael autoexposure tint low reserved ff devid_n devid_n ones complement of devid (register 0x0a) 7ff - 100 reserved reserved for row timing generators. table 8-1. register map (continued) addr name 7 6 5 4 3 2 1 0 description bit # name dir default function 15:12 reserved 0 11:0 rows rw 12 starting row address bit # name dir default function 15:12 reserved 0 11:0 cols rw 12 starting column address bit # name dir default function 15:12 reserved 0 11:0 rownum rw 1555 number of active pixels in each column
cyiwosc3000a a document #: 38-19009 rev. *e page 16 of 37 rownumh and rownuml are a regist er pair that make up a twelve-bit register . the upper 4 bits of rownumh are reserved. the lower 4 bits of rownumh make up the 4 most significant bits of the number of active columns and rownuml make up the low eight bits. the rows and cols register specify the upper left corner of the active window. this register specifies how high the active window should be. bit zero should always be zero to insure whole bayer patterns are in the window. the number of rows also affects the frame rate. the fewer columns that are read out, the higher the frame rate. 8.2.4 colnumh(06) & colnuml(07) colnumh and colnuml are a register pair that make up a twelve-bit register. the upper 4 bits of colnumh are reserved. the lower 4 bits of colnumh make up the 4 most significant bits of the number of active pixels in each column and colnuml make up the low eight bits. this register specifies how wide the active window should be. bit zero should always be zero to ins ure whole bayer patterns are in the window. changing the number of columns does not alter the frame rate. the column timing remains constant regardless of the number of columns programmed in the colnum register. however, the dat a rate will be reduced as only the columns requested will be clocked out on the pixel data bus. 8.2.5 hblankh(08) & hbankl(09) hblankh and hblankl are a register pair that make up an el even-bit register. the upper 5 bits of hblankh are reserved. the lower 3 bits of hblankh make up the 3 most significant bits of the duration of horizontal blanking for each row and hblankl makes up the low eight bits. hblank can be made larger to lower the data rate however, it will decrease the resolution of the integration time (tint) so it is recommended to keep hblank at its default value. hblank must be a minimum of tbd clks to allow for quiet time during certain sampling periods of each row. 8.2.6 devid(0a) the devid register provides a unique indicator for software to determine the capabilities of the ima ger. the CYIWOSC3000AA imager value is 0x4f (ascii ?o?). the ones-complement of devi d is also available at address 0xff. this can be used to verify a ?signature? so the software knows what type of imager it is connected to. 8.2.7 version(0b) the version register is an eight- bit register that specifies what version of silicon this chip is. some features may not be pre sent in various versions of the silicon. 8.2.8 vblankh(0c) & vblankl(0d) vblankh and vblankl are a re gister pair that make up a twelve-bit register. vblank is the number of rows of vertical blanking time. the register is a twelve-bit register to allow for a wide range of frame rates. each vblank value decreases the frame rat e by one row. the minimum number of rows is 8, whic h are required to perform column fpn calculations. 8.2.9 inttimeh(0e) & inttimel(0f) bit # name dir default function 15:12 reserved 0 11:0 colnum rw 2067 number of active pixels in each row. bit # name dir default function 15:11 reserved 0 10:0 hblank rw tbd duration of hblank. bit # name dir default function 7:0 devid r 0x4f device id bit # name dir default function 7:0 version r 1 silicon version bit # name dir default function 11:0 vblank rw 16 duration of vblank. bit # name dir default function 11:0 inttime rw 240 duration of integration time (exposure time).
cyiwosc3000a a document #: 38-19009 rev. *e page 17 of 37 inttimeh and inttimel are a register pair that make up a twelve-bit register. the integration time is the number of row times that the pixels are exposed before being read out. note that the inttime register may be updated at any time during the frame. it is only used by the timing logic when at a speci fic point in each frame (when the tint reset pointer is at the first row of bottom dark pixels). the inttimeh register should utili ze the sync register so that it only gets updated during vsync. no te that when autoexposure is enabled, this register is ignored. when the inttime value is increased, it must only be increased by the number of bottom dark rows plus the number of vblank rows or a split frame may be output. inttime can be decreased by any amount from one frame to the next. when inttime is increased by a large number (the image pans from a bright to a dark scene), the user has the option of accepting the split fram e or increasing tint by only the amount listed above. you can also increase the number of vblank rows to allow a rapid increase in the number of rows. 8.2.10 rgainh(10 ) & rgainl(11) the red gain is applied only to red pixels. each pixel is digitally multiplied by the rgain value. the gain value is a 4.8 fixe d point integer thus the red pixels can be digitally gained up by a factor of 16. by default the multiplication factor is 1 (0x10 0). if the result of the multiplication is greater than 4095, then the value is saturated to 4095. 8.2.11 grgainh(12) & grgainl(13) the gr gain is applied only to green pixels on a red ro w. each pixel is digitally multiplied by the grgain value. 8.2.12 gbgainh(14) & gbgainl(15) the gbgain is applied only to green pixels on a blue row. each pixel is digitally multiplied by the gbgain value. 8.2.13 bgainh(16) & bgainl(17) the bgain is applied only to blue pixels. each pixel is digitally multiplied by the bgain value. 8.2.14 gain(18) the enb bit of he gain register must be a 1 for the following four gain registers to have an effect on the image data. when enb is zero, the gain multipliers are bypassed and the data is passed through unaltered. 8.2.15 roixsh(20) & roisxl(21) the roixsh and roixsl registers form a twelve-bit register. the roixs register is the starting column of the region of interest . the roi is the area of the active array where statistics will be collected. the roi can either be inside or outside of the rect angle defined by the roi registers. the roi does not include the dark pixels. bit # name dir default function 11:8 rgainh rw 0x01 red gain integer 7:0 rgainl rw 0 red gain fraction bit # name dir default function 11:0 grgain rw 0x100 green-red gain bit # name dir default function 11:0 gbgain rw 0x100 green-blue gain bit # name dir default function 11:0 bgain rw 0x100 blue gain bit # name dir default function 0 enb rw 0 0 = bypass digital gain 1 = enable digital gain bit # name dir default function 11:0 roisx r/w 0 region of interest start x
cyiwosc3000a a document #: 38-19009 rev. *e page 18 of 37 8.2.16 tintinch(1e) & tintincl(1f)) the enb bit of the tintinc register enables the 50/60 flicker mode for the auto exposure unit. when tintinc mode is enabled, tint is forced to be the nearest increment of the value programmed in tintinc. if the auto exposure unit wants to set tint to a value less than tintinc, it will be set to exactly the desired value. if the auto exposure unit wants to set tint to a value la rger than tintinc, then it will only set tint to be an integer multiple of tintinc. tintinc must be programmed with the number of row times that corresponds to either 1/100th of a second or 120th of a second. this will eliminate flicke r that is observed when operating the camera u nder fluorescent lights. 8.2.17 roixsh(20) & roisxl(21) the roixsh and roixsl registers form a twelve-bit register. the roixs register is the starting column of the region of interest . the roi is the area of the active array where statistics will be collected. the roi can either be inside or outside of the rect angle defined by the roi registers. the roi does not include the dark pixels. 8.2.18 roiwxh(22) & roiwxl(23) the roiwxh and roiwxl registers form a twelve-bit register. the roiwx register is the number of columns of the region of interest plus 1. a value of ze ro will result in an roi of 1 co lumn. the width should always be programmed to include whole baye r patterns. thus, roiwx should be odd. 8.2.19 roiysh(24) & roiysl(25) the roiysh and roiysl registers form a twelve-bit register. the roiys register is the starting row of the region of interest. 8.2.20 roiwyh(26) & roiwyl(27) the roiwyh and roiwyl registers form a twelve-bit register . the roiwy register is the num ber of rows of the region of interest plus 1. 8.2.21 aemaxh(28) & aemaxl(29) aemax sets the maximum value for tint expressed in number of rowtimes. when auto exposure mode is enabled, this value forces tint to always be less than or equal to this value. auto exposure mode always has the upper 4 bits of tint to be zero. 8.2.22 aeminh(2a) & aeminl(2b) bit # name dir default function 15 enb r/w 0 0 = disable tint increment 1 = enable tint increment 14:12 r 0 reserved 11:0 tintinc r/w 0 number of rows that tint can change by bit # name dir default function 11:0 roisx r/w 0 region of interest start x bit # name dir default function 11:0 roiwx r/w 2063 width of the region of interest end x+1 bit # name dir default function 11:0 roiys r/w 0 region of interest start y bit # name dir default function 11:0 roiwy r/w 1551 width of the region of interest end y +1 bit # name dir default function 11:0 aemax rw 0 aemax is the maximum allowed value for tint (integration time) expressed in number of row-times. bit # name dir default function 11:0 aemin rw 0 aemin is the minimum allowed value for tint (integration time) expressed in number of row-times.
cyiwosc3000a a document #: 38-19009 rev. *e page 19 of 37 aemin sets the minimum value for tint expressed in number of rowtimes. when auto exposure mode is enabled, this value forces tint to always be more than or equal to this value. 8.2.23 aeavgh(2c) & aeavgl(2d) aeavg is the desired image average. if the cu rrent image average is below this value, then tint will be increased. if the curre nt image average is below this value then tint will be decreased. 8.2.24 exposure(2f) autoenb causes the value of tint to be computed based on the current image average. this is a relatively crude automatic exposure control mode. the image average is com puted in the roi specified in the roi registers. inside determines whether the image statistics are to be computed from the area inside the roi or outside. fast determines the rate of adjustment of the auto exposure. when fast=1, the exposure control is adjusted each frame to ? of the difference between the current tint and the calculated new tint. when fast=0, tint is adjusted by 1/8 th of the difference. 8.2.25 blklvlh(30) & blklvll(31) in normal operation, blklvl is automatically computed by accumulating the value of the first 8096 pixels in the top dark rows. this value is then subtracted from each pixel to remove the dark current if darkmode enb = 1. the automatic computation of blklvl can be overridden by setting the override bit. in this case, blklvl must be written with the desired black level to be subtracted. the automatic black level is enabled by the enb bit in the darkmode register. 8.2.26 darkmode(32) enb enables an fpn mode where the dark rows across the top of the imager are averaged to compute a black level. the black level is then subtracted from each pixel in the rest of the cu rrent frame. the dark values are clipped to acceptable values bef ore being accumulated. the digital gain should be adjusted slightly depending on the black level being subtracted to insure that saturated pixels remain saturated. the black level can be manually controlled with the blklvl register. bit # name dir default function 15:4 aeavg rw 0x800 aeavg is the desired image average. bit # name dir default function 7 autoenb rw 0 0 = manual exposure control 1 = automatic adjustment of tint 6 inside rw 0 0 = statistics are computed inside the roi 1 = statistics are computed outside of the roi 0 fast rw 0 0 = normal rate of exposure control 1 = fast adjust of tint bit # name dir default function 0 override rw 0 0 = automatic black level computation 1 = override black level 15:4 blklvl rw 0 black level subtracted from each pixel when enabled. pixnew = pix ? blklvl bit # name dir default function 7 enb rw 0 0 = disable black level subtraction 1 = enable black level subtraction 6 status r 0 = dark subtraction working 1 = dark subtraction error 6:3 r 0 reserved 2:0 mod rw 000 000 = accumulate 8096 pixels for dark current 001 = 4096 pixels 010 = 2048 pixels 011 = 1024 pixels 100 = 512 pixels 101 = 256 pixels 110 = 128 pixels 111 = 64 pixels (not recommended)
cyiwosc3000a a document #: 38-19009 rev. *e page 20 of 37 the status bit is a flag indicating that there are not enough da rk pixels to properly compute the dark current in the current operating mode. if status = 1, then mod should be increased until status is 0. otherwise the dark current subtraction will be incorrect. typically mod will need to be increased when binning or subwindowing in x. the mod bits allow for a few different numbers of pixels to be accumulated. when the abin register is set to combine pixels in the horizontal direction, the mod bits must be changed to reduc e the number of pixels used for the dark current subtraction. there must be at least the desired number of dark pixels or t he calculation will be incorrect. w hen hbin by 2 is enabled, there are only 1040 dark pixels per row and mod must be set to 1. addi tional dark rows can also be enabled with the darktop register. 8.2.27 fpnmode(33) fixed pattern noise removal is enabled with the fpnmode register. fpnflush mode is typically used to quickly stabilize the column fpn data when changing modes, especially when switching to or from one of the binning modes. when fphflush is a 1, the imager does not output data but will instead output black so the back-end processor will have to discard all frames when fp nflush is a 1. it it recommended to leave fphnflush a 1 for one frame time to insure the column fpn data is stable. testsigcol selects an internal voltage signal as the refere nce signal for column fpn data collections. when testsigcol is a zero, the data is sourced from one of the bottom dark rows instead of the internal voltage. it is recommended to keep this signal as a 1. fpncolenb enables a sophisticated column noise removal algorithm. each column has a value that is sampled from a test voltage and averaged across all rows of vertical blanking. this accumulated value is stored for each column and is subtracted from each pixel in that column. colmax enables maximum mode fo r column fpn removal. in this mode, the ma ximum value of the columns is searched for and kept in a register. each pixel is then computed with the following equation: pixel_out = pixel_in + fpnmax ? fpncol note that this mode is susceptible to outlyers in column fpn data and will tend to oversaturate pixels as it adds a significant offset. this offset is normally removed by the dark current removal logic later in the image pipeline. when colmax is 0, then average mode column fpn is enabled. this is the recommended mode of operation. in average mode, the average value of all of the columns is added to each pixel and the value in the fpn ram is subtracted from each pixel. in this mode, pixels are saturated both in the max and min direction. pixel_out = pixel_in = fpnavg ? fpncol colclip is only used in average mode and lowers the saturation clip value for each pixel by the following equation: saturate_max = 0xfff ? fpnavg collpf is normally left at its default value of 1. the low-pass filter insures that the column fpn data is accumulated slowly across many frames to compensate for changes in temperature or voltage. collpf should be cleared to 0 to initialize the column fpn data for at least 1 frame. otherwise it may take several seconds fo r the column fpn data to st abilize to its correct value. displaycol is for testing purposes only and this bit should alwa ys remain 0 in normal operation. when 1, the values from the colfpn ram are output on the first row of vertical blanking. bit # name dir default function 7r0reserved 6 fpnflush rw 0 0 = normal operation 1 = rapid stabilizing of column fpn data 5 testsigcol rw 1 0 = use dark row for colfpn data 1 = use testsig for colfpn data 4 displaycol rw 0 0 = normal operating mode 1 = output test column data as pixels 3 colmax rw 1 0 = average mode column fpn 1 = max mode column fpn 2 collpf rw 1 0 = column fpn low-pass filter disabled 1 = column fpn low-pass filter enabled 1 colclip rw 1 0 = disable clipping in average mode column fpn 1 = enable clipping in average mode column fpn 0 fpncolenb rw 0 0 = disable column fixed pattern noise reduction 1 = enabled column fpn reduction
cyiwosc3000a a document #: 38-19009 rev. *e page 21 of 37 8.2.28 abin(35) the abin register sets the analog binning mode. 8.2.29 hbin(36) the hbin register enables and sets the value for horizontal binning mode or skip mode. in effect, hbin sets the horizontal zoom factor. there are two stages of bin/skip. the first stage can bin by 2, 3, or 4 pixels. the sec ond stage can only bin by 2 or 3 . each stage can either bin or skip independently. the bin1/2 bits de termine if subsampling (skip) or binning it to be performed. subsampling requires less power but may result in a sparkling of the image if details line up with the active pixel or not. bin ning averages many pixels together which is a fairly compute intensive operation and thus requires more power. horizontal binning is done digitally. the weight bit is only used if binning is enabled for x3 or x4. if x3 binning is enabled, then a weighting is applied so that t he average can be obtained with a simple shift operation instead of a divide. when weight = 1, this weighting is changed for red or green-blue pixels and for green?red or bl ue pixels. this shifts the weight from the center of the superpixel to a more corre ct spatial weighting. in bin x4 mode, if weight = 1 then a weighting is applied. weight has no effect on bin x2. the sum bit is also only used when binning is enabled. when sum=1, then the result of the bin is not shifted down after adding the pixels together. this results in a 2, 3, or 4x gain which can improve images in low-light conditions. 8.2.30 vbin(37) bit # name dir default function 7r0reserved 6:4 hbin rw 000 000 = 1:1 (no binning) 001 = 2:1 010 = reserved 011 = 4:1 1xx = reserved 4r0reserved 2:0 vbin rw 000 000 = 1:1 (no binning 001 = 2:1 010 = 3:1 011 = 4:1 100 = 6:1 (bin by 3 and subsample by 2) all other values are reserved bit # name dir default function 7 sum rw 0 0 = average the binned pixel 1 = sum the binned pixels 6 bin2 rw 0 0 = subsample stage 2 1 = bin 5:4 hbin2 rw 00 00 = no 2 nd stage binning/skipping 01 = 2 nd stage bin/skip by 2 10 = 2 nd stage bin/skip by 3 3 weight rw 0 0 = 1:2:1 weighting for binx3 1 = spatial based weighting for bin x3 and x4 2 bin1 rw 0 0 = subsample stage 1 1 = bin 1:0 hbin1 rw 00 00 = no horizontal binning/skip?disabled 01 = bin/skip every 2 pixels 10 = bin/skip every 3 pixels 11 = bin/skip every 4 pixels bit # name dir default function 7 sum rw 0 0 = average the binned pixel 1 = sum the binned pixels 6 bind rw 0 0 = subsample digital 1 = bin digital
cyiwosc3000a a document #: 38-19009 rev. *e page 22 of 37 the vbin register enables and sets the value for vertical binning mode. vertical binning causes the number of vertical pixels t o be averaged together. horizontal and vertical binning as normally set to the same value at the same time. binning causes the pixels of the same color to be averaged together. this allows a full field-of-view image at a lower resolution to be output wit hout the ?sparkling? effects of a sub-sampled windowing mode. subsam pling will significantly increase the frame rate and reduce the overall power consumption. the choice of binning or subsampling is independent for both the analog and digital stages. there are two stages of vertical binning, analog and digital. analog binning is done in the analog domain and digital binning i s done digitally. analog binning requires a number of changes to the timing control registers. the weight and sum bits have the same meaning here as they do for digital binning (see the hbin register) but only apply to the digital binning stage. the analog stage is not affected by ei ther the weight or sum bits. independent bits are provided her e but typically they should be set to the same value as the hbin register. 8.2.31 pixrepl(38) pixreplenb enables the pixel replacement algorithm that hides normal defects in the image array. pixel replacement must be turned off when binning or boosting. pixel replacement is not n eeded when binning since multiple pixels are averaged together. the maximum error a bad pixel can contribute is only ? of a pixel in bin by 3 where the bad pixel is in the center and thus wei ghted 2x. do not turn off pixel replacement when subsampling. threshold enables a 4-bit threshold mode for the pixel repl acement algorithm. when threshold is a one, the difference between the current pixel and the minimum or maximum of its adjacent same-color pixels must have a magnitude that extends into the upper 4 bits of the 12-bit pixel. thus, for a pixel to be replaced, the pixel difference must be more than 1/16th of a the full scale. this insures that only significantly bad pixels are re placed. when threshold mode is a zero, then any pixel that is greater than the maximum or less than the minimum is replaced . this occurs many thousands of time in a typical image. 8.2.32 datafmt(39) 5:4 vbind rw 00 00 = no digital binning 01 = digital bin by 2 10 = digital bin by 3 3 weight rw 0 0 = 1:2:1 weighting for binx3 1 = spatial based weighting for digital bin x3 2 bina rw 0 0 = subsample analog 1 = bin analog 1:0 vbina rw 00 00 = no vertical binning?disabled 01 = bin every 2 pixels together 10 = bin every 3 pixels together 11 = bin every 4 pixels together bit # name dir default function bit # name dir default function 1 threshold rw 0 0 = disable threshold mode 1 = enable threshold mode 0 pixreplenb rw 0 0 = disable pixel replacement 1 = enable pixel replacement bit # name dir default function 7 embdsync rw 0 0 = disable embedded sync 1 = enable embedded sync 4 cpdfmt rw 0 0 = companding format 1 1 = companding format 2 3 configrow rw 0 0 = normal operation 1 = include the configuration row data 2 compand rw 0 0 = normal operation 1 = compand the 12-bit pixel to 8-bits 1 8bmode rw 0 0 = normal operating mode 1 = shift pixdat down by 4 bits 0 darkenb rw 0 0 = only active pixels are read out 1 = all pixels are read including all dark pixels
cyiwosc3000a a document #: 38-19009 rev. *e page 23 of 37 embdsync enables embedded sync information to be embedded in the pixel data stream. when embdsync is disabled, the hsync and vsync pulses must be used to identify when a fram e or row begins and ends. when embdsync is enabled, then the sync signals are identified when a pattern of 0xff, 0x00, 0x00 is seen in the pixel stream. any color values that are 0xff are clipped to 0xfe to insure that the data is not seen as a sync indicator. following the sync pattern the following values in dicate what sync is present ? 0x00 = row start, 0x01 = row end, 0x02 = frame start, 0x03 = frame end. configrow enables a packet of data to be output on the pixdata bus during vertical blanking. the data is embedded in the last row of vertical blanking and is prefixed with the code 0x ff, 0x00, 0x00, 0x0c. the data is always output as bytes of data regardless of the setting of 8bmode. thus, when 8bmode is 0, t he data is broken up as 3 bytes of data every 2 pixels (12 bits). when 8bmode is 1, then the config row matches the data width. the following table lists the bytes of data in the config row: compand enables a 12-bit to 8-bit non-linear companding of the data. this enhances the dynamic range but allows the processor to work with 8-bit pixels. normally the 8-bits are ou tput on the most significant 8-bits unless 8bmode is 1. there ar e two companding functions provided. cmpfmt selects between these two formats. bit # name value function 1?3 sync 0xff 0x00 0x00 sync indicator. note that this pattern can occur in the image data unless embedded sync is enabled. 4 type 0x0c config row indicator 5?6 length 48 number of bytes following these 2 bytes. the most significant 8-bits are sent first. 7 version 0 version of the configuration row 8 key 0x03 frame count key 9?10 framecount 16-bit incrementing fr ame count. msbs are sent first. 11 key 0x06 integration time key 12?13 tint integration time used on this frame. see the inttime register for more details. 4 msbs are always zero. 14 key 0x2e image average red key 15?16 avgred image average of the red channel. see the ravg register for more details. 17 key ox2f image average greenred key 18?19 avggrr image average of the greenred channel 20 key 0x30 image average greenblue key 21?22 avggrb image average of the greenblue channel 23 key 0x31 image average blue key 24?25 avgblue image average of the blue channel 26 key 0x32 image average luminance key 27?28 avglum image average of the sum of all 4 color channels 29 key 0x33 black level key 30?31 blklvl black level that was subtracted from this frame. see the blklvl register for more details 32 key 0x34 noise variance key 33?34 noisevar noise variance computed for this frame. see the noisevar register for more details. 35 key 0x34 rgain key 36?37 rgain red gain. 4 msbs are always 0 38 key 0x34 grgain key 39?40 grgain greenred gain. 4 msbs are always 0. 41 key 0x34 greenblue key 42?43 gbgain greenblue gain. 4 msbs are always 0 44 key 0x34 bgain key 45?46 bgain blue gain. 4 msbs are always 0. 47?48 endpkt 0x00 2 bytes of zero
cyiwosc3000a a document #: 38-19009 rev. *e page 24 of 37 companding format 1: modified a-law companding format 2: simple 2-segment 8bmode simply shifts the pixdat bus to the right by 4 bits. th is allows a linear mapping of 12-bit to 8-bits by simply dividing the pixel value by 16. darkenb enables the dark pixels to be output on the pixdat bus as if they were part of the image. this mode is usually used for testing purposes but can be used to improve noise reduction if black-level correction is turned off and instead the functio n is performed by the back-end processor. 12-bit original 8-bit 12-bit recovered 000000wxyzab 00wxyzab 000000wxyzab 000001wxyzab 010wxyza 000001wxyza0 00001wxyzabc 011wxyza 00001wxyza00 0001wxyzabcd 100wxyza 0001wxyza000 001wxyzabcde 101wxyza 001wxyza0000 01wxyzabcdef 110wxyza 01wxyza00000 1wxyzabcdefg 111wxyza 1wxyza000000 compand mode 1 0 32 64 96 128 160 192 224 256 0 256 512 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 12-bit original 8-bit 12-bit recovered 00000wxyzabc 0wxyzabc 00000wxyzabc wxyzabcdefgh 1xyzaabc 1wxyzabc0000 compand mode 2 0 32 64 96 128 160 192 224 256 0 256 512 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840
cyiwosc3000a a document #: 38-19009 rev. *e page 25 of 37 8.2.33 syncpol(3a) the syncpol register provides polarity co ntrol of the pixel da ta output pins. vsync will be hi gh during vertical blanking time when vsyncpol = 1. hsync will be high during the horizontal blanking time when hsyncpol = 1. the edge that pixdata transitions on can be selected with the pclkpol bit. normally pclkpol will want to be zero which sets the rising edge of pixclk in the middle of a clock period w here pixdata is stable. this will insure su fficient setup and hold times across a flex cable to the back-end processor. if the back-end processor clocks data in on the falling edge of the clock or if there is a sig nificant amount of delay of pixclk, pclkpol may be programmed with a 1. datval = 1 changes the functionality of the hsync pin to be a ?data valid? signal instead of a synchronization pulse. this mode is normally used when mod = 11 as pixclk is free-running and the back-end processor needs a signal to tell it when valid data is present on the pixdata bus. the mod bits provide four different clocking modes that provide different options for clocking data into the back-end processor . the simplest mode is mod=00 where pixclk runs only when there is valid data on the pixdata bus. the problem with this mode is that there are no clocks during hsync and vsync and many back-end processors need a few clocks during this time. if the back-end processor needs to clock in hsync and vsync, use mod = 01. this mode provides one extra clock each row at the end of a row. this insures that hsync and vsync are samp led by the back-end processor. note that this will increase the size of the image by 1 pixel and this pixel must be ignored when doing image processing. if pixclk needs to free-run during the syncs, use mod = 10. in th is mode it is assumed that the back-end processor knows that it does not need to clock in the data when hsync is active. note that pixclk will skip some pulses during the active portion of a row if binning is enabled. if pixclk needs to always free-run, then use mod = 11. in this mode pixclk is the same as clk except that it is delayed by the internal clock buffers to match the output delay on the pixdata bus. in this mode datval is normally set to 1 so that the back-end processor knows which pixels have valid data or not. some back-end processors are able to compute where the valid pixels are in a row but care must be taken to properly align the data. 8.2.34 tstptn(3b) the tstptn register enables a test pattern to be output. there are three test patterns available. the standard smpte color bars pattern, a 12-bit incrementing gradient in x and a 12-bit incrementing gradient in y. bit # name dir default function 7 vsyncpol rw 0 0 = vsync active low 1 = vsync active high 6 hsyncpol rw 0 0 = hsync active low 1 = hsync active high 5 extraclk rw 0 0 = pixlck only when pixels are present 1 = one extra pixclk when a row starts and ends 4 datval rw 0 0 = pixclk only clocks when hsync is inactive; hsync is a sync pulse 1 = pixclk clocks continuously ; hsync is a datval pulse 3 pclkpol rw 0 0 = pixdata transitions relative to the falling edge of pixclk 1 = pixdata transitions relative to the rising edge of pixclk 2 reserved r 0 1:0 mod rw 00 00 = pixclk on valid data only 01 = pixclk on valid data and on rowend 02 = pixclk on valid data and when hsync inactive 03 = pixclk freeruns bit # name dir default function 2:0 tstptn rw 00 000 = test pattern disabled 001 = smpte colorbars 010 = incrementing gradient in x 011 = incrementing gradient in y 1xx = reserved
cyiwosc3000a a document #: 38-19009 rev. *e page 26 of 37 8.2.35 flip(3c) the mirror bit is used to reverse the order that pixels are re ad out which allows the image to be mirrored in the x dimension. in this case, the column counter is decremented instead of being incremented. note that the dark rows on the left and right sid e of the image are still read out first so they can be used for ro w fpn reduction. cols should be programmed with the rightmost red column of active pixels to insure proper bayer pattern alignment. the flip bit is used to reverse the order that rows are read out of the imager. when flip = 1, then the row counter is decremented instead of being incremented. this allows the ima ge to be flipped in the y dimension under software control. note that the top dark rows are still read out first. rows should be programmed with the bottom red row of active pixels to maintain proper bayer pattern alignment. 8.2.36 darktoph(3e) & darktopl(3f) the darktop registers make up a 12-bit register. each bit of the register enables the respective dark row at the top of the imager. if the bit is a 1, then the row is used in the dark cu rrent calculation. if the bit is 0, then the row is ignored. dark top[0] corresponds to row 0, darktop[1] corresponds to row 1 and so on. at least 4 rows must be turned on to properly compute the dark current. by default, the middle 4 rows are turned on wh ich typically are the best for computing the dark current. 8.2.37 gpio(60) the gpio register controls the state of the gpio pin. the gpio pin is a general purpose io pin that is controlled via this regi ster. the default state of the gpio pins is for a weak pulldown resist or to pull the pin to ground and insure a proper logic level ev en if the pin is left unconnected. the level bit is used to set the output level of the gpio pi n when tristate is 0. note that when this bi t is read, it reflects the current level on the gpio pin and not the value programmed in the l evel bit of this regi ster. thus, when tristate is a 1, this bit is effectively a read-only bit that is the current logic level of the gpio pin. the tristate bit is used to program the gpio pin as either an input or an output. when tristate = 0, the gpio pin is an output and the value programmed in the level bit will be driven ont o the gpio pin. if tristate = 1, the gpio pin is an input. the keep bit will enable a weak bus keeper on the gpio pin. if tristate = 1 and pullenb = 0, this pin should be programmed as a 1 to insure a valid logic level is maintained on the gpio pin. gpio should not be allow to float. the inenb bit enables the input. if tristate=1 this bit should be a 1. this pin also gates the bus keeper function so it has to be 1 for the bus keeper to be enabled. bit # name dir default function 1 mirror rw 0 0 = normal operation 1 = mirror image in x 0 flip rw 0 0 = normal operation 1 = flip image in the y dimension bit # name dir default function 11:0 darktop rw 0x0f0 bit mask of valid rows to use for dark current statistics bit # name dir default function 7 level rw 0 write = level dr iven onto gpio if enabled read = level on the gpio pin 6 tristate rw 1 0 = drive l evel onto the gpio pin 1 = gpio is tristate 5 keep rw 0 0 = bus keeper is disabled 1 = bus keeper enabled 4 inenb rw 1 0 = input is disabled 1 = input is enabled 3 pulldir rw 0 0 = pull down 1 = pull up 2 pullenb rw 1 0 = pull-up/down resistor disabled 1 = pull-up/down resistor enabled 1drv rw 1 0 = 8 ma drive 1 = 2 ma drive 0 vsel rw 0 0 = vddio 1.8v 1 = vddio 2.8?3.3v
cyiwosc3000a a document #: 38-19009 rev. *e page 27 of 37 pulldir determines the direction of the optional pull-up resistor. 0 = pull-down, 1 = pull-up. the pullenb bit enables an on-chip pull-up or pull-down resistor . pulldir selects if a pull-up or pull-down is selected. drv selects the drive strength of the output driver. 0 = 8 ma nomi nal drive, 1 = 2 ma low-power drive. the 2-ma drive strength is recommended to keep power consumption low. the vsel bit must be programmed to match the power supply that vd dio is connected to. if vddio is connected to a 1.8v supply, then vsel must be programmed with a 0. if vd dio is connected to a 2.8 to 3.3v supply, then vsel must be programm ed with a 1. 8.2.38 i 2 cio(61) the i 2 cio register controls the io pin settings of the sbia3, sclk and sdat i 2 c pins. sclk and sbia3 are input only pins but each pin has its own control bits for a pull-up or pull-down resistor. sclk and sdat share the same pull-up/down controls. sdat is a bidirectional pin and has an additional 2 control bit for selecting the io voltage and drive strength as well as a weak bu s keeper function. 8.2.39 pclkio(62) the pclkio register controls the io pin settings of the pixclk pin. pixclk can operate at up to 48 mhz so individual control of the io pin is provided to meet the timing and drive strength needs of the application. the tristate bit will tri-state the p ixclk pin. when pixclk is tri-state, the keep or the pullenb bit must be set or an external pull-up resistor must be used to insure that pixclk does not float or the pin will draw excess power. t he drv and vsel bits select the drive strength and vddio voltage respectively. bit # name dir default function 7r0reserved 6 pdira3 rw 0 0 = sbia3 pulled down 1 = sbia3 pulled up 5 pea3 rw 1 0 = disable pull-up/down on sbia3 1 = enable pull-up/down on sbia3 4 keep rw 0 0 = disable bus keeper on sdat 1 = enable bus keeper on sdat 3 pulldir rw 1 0 = pull down on sclk, sdat 1 = pull up on sclk, sdat 2 pullenb rw 1 0 = pull-up/down resistor disabled on sclk, sdat 1 = pull-up/down resistor enabled on sclk, sdat 1 drv rw 1 0 = 8 ma drive on sdat 1 = 2 ma drive on sdat 0 vsel rw 0 0 = vddio 1.8v on sdat 1 = vddio 2.8?3.3v on sdat bit # name dir default function 7r0reserved 6 tristate rw 0 0 = pixclk enabled 1 = pixclk tri-stated 5 keep rw 0 0 = bus keeper disabled 1 = bus keeper enabled 4r1reserved 3 pulldir rw 0 0 = pull down 1 = pull up 2 pullenb rw 0 0 = pull-up/down resistor disabled 1 = pull-up/down resistor enabled 1 drv rw 0 0 = 8 ma drive on pixclk 1 = 2 ma drive on pixclk 0 vsel rw 0 0 = vddio 1.8v on pixclk 1 = vddio 2.8?3.3v on pixclk
cyiwosc3000a a document #: 38-19009 rev. *e page 28 of 37 8.2.40 pixio(63) the pixio register controls the io pin settings of the d[11:0], hsync and vsync pins. the tristate bit will tri-state the pins. when the pins are tri-state, the keep or the pu llenb bit must be set or an external pull- up resistor must be used to insure tha t the pins do not float or there will be excess power consumed. the drv and vsel bits select th e drive strength and vddio voltage respectively. 8.2.41 pwrctl(70) the pwrctl register controls the power consumption of the CYIWOSC3000AA imager. the imager powers-up in normal active mode ready to begin full operation once the registers have been initialized. the default state of pwrctl corresponds to power mode 1 (active). power mode 2 (standby) is achieved by setting the triio bits in the pclkio and pixio registers. this tri-states the io pins and reduces power consumption. power consumption is only slight ly reduced however the imager is continuing to accumulate statistics and ready to take an image on the very next frame. power mode 3 (full standby) is achieved by setting the imgdis bi t to a 1. in this mode, the imager is turned off and no video data is produced and no statistics are computed. all registers re tain their current state and are ready to begin image capture once imgdis is cleared to 0. power consumption is reduced as the ti ming signals to the image array are static and no data is flowing through the digital logic. the pix bus ios are static as well. no te that since no statistics are being computed, the exposure c ontrol and fpn algorithms will need several frames to stabilize before a valid image is ready to capture. 8.2.42 reset(7e) writing a 0x52 to the reset register causes the entire chip to be reset. writing any value other than 0x52 (ascii ?r?) has no effect. note that the reset takes place as soon as the i 2 c ack bit is started. thus, the ima ger will not ack the data byte of the i2c command as it is now in reset and waiting for an i 2 c start command. bit # name dir default function 7r0reserved 6 tristate rw 0 0 = outputs enabled 1 = tri-stated 5 keep rw 0 0 = bus keeper disabled 1 = bus keeper enabled 4r1reserved 3 pulldir rw 0 0 = pull down 1 = pull up 2 pullenb rw 0 0 = pull-up/down resistor disabled 1 = pull-up/down resistor enabled 1drv rw 1 0 = 8 ma drive 1 = 2 ma drive 0 vsel rw 0 0 = vddio 1.8v on pixclk 1 = vddio 2.8?3.3v on pixclk bit # name dir default function 7:1 r 0 reserved 0 imgdis rw 0 0 = normal operation 1 = disable image sensor logic bit # name dir default function 7:0 reset w write a 0x52 to reset the entire chip.
cyiwosc3000a a document #: 38-19009 rev. *e page 29 of 37 8.2.43 sync(7f) critical configuration registers have a shadow register in thei r write path. this allows these registers to be loaded with a ne w value but it won't take effect until just before the next frame begins. when enb is 0, the shadow register is disabled and acce ss is direct to the register. note that changing many of the row/column registers during an active frame time will cause a bad fra me to be output. when enb is 1, then any write to a register with a shadow register causes the write to be stored but not take eff ect until the nextvsync bit is a 1 and vsync begins. note that register reads always come from the currently active register. when enb = 1, after you write to a register, if you immediately read the register you will get the old value, not the value you just wrote. once nextvsync = 1 and vsync has occurred, then the new value can be read from the register. the vblank bit may be used to update a small number of regist ers during the vertical blanking time. this is a read only bit. software can simply poll this bit and wait until it is a one (o r transitions to a one) and then write a few registers directly without causing bad frames. once the enb and the nextvsync bit are set, no register writes should be performed until the registers have been updated. the enb bit will be cleared to 0 when the registers are updated. ther e is a small chance that a write to a register will happen jus t as the other registers are being updated at vsync and the write conflict will result in unpredictable operation. usage examples: 1. initial power-up a. the imager is currently off and we wish to configure the registers as quickly as possible. b. enb = 0, nextvsync = x (don't care but usually 0). c. write all configuration registers d. enable the back-end processor to begin searching for a vsy nc pulse to begin processing frame data. the first frame may be a partial frame with bad data. 2. change from video sub-windowed mode to full image capture mode a. enb = 1, nextvsync = 0 b. write all registers that need to be updated for the new capture mode c. nextvsync = 1 d. wait until nextvsync = 0, which indicates that the registers have been updated. the next frame should begin immediately and be in the new format. do not write to any other registers while waiting for nextvsync to change to 0. note: registers in table 8-1 labeled with a 1 are controlled by the sync bit. note that many of the other registers are effectively synced as they are only used by internal logic at specific time s during a frame. see the individual register descriptions for m ore details. bit # name dir default function 7 enb rw 0 0 = immediate access to all registers 1 = enable synchronization mode this bit is automatically cleared once the vsync has updated the registers 6 nextvsync rw 0 0 = no updates to the registers 1 = update all registers on the next vsync. this bit is automatically cleared once the vsync has updated the registers. 5 vblank r 0 = not currently in vblank 1 = imager is currently in vblank
cyiwosc3000a a document #: 38-19009 rev. *e page 30 of 37 8.3 status registers 8.3.1 gravgh(80) & gravgl(81) the gravg registers make up a sixteen-bit register split across tw o 8-bit registers. the value is the average intensity value i n a 12.4 fixed point format for all green pixels on the red row in th e area defined by the roi register s. the upper twelve bits are the integer portion and the lower four bits provide a fractional valu e. this register is updated at the end of the active pixels an d before vertical blanking. the register always contains a valid value of the most recent frame. 8.3.2 gbavgh(82) & gbavgl(83) the gbavg registers are the average intensity value for all green pixels on the blue row in the area defined by the roi registe rs. this register is updated at the end of the active pixels and be fore vertical blanking. the register always contains a valid val ue of the most recent frame. 8.3.3 ravgh(84) & ravgl(85) the ravg registers are the average intensity value for all red pixe ls in the area defined by the roi registers. this register i s updated at the end of the active pixels and before vertical blanking. the register always contains a valid value of the most re cent frame. 8.3.4 bavgh(86) & bavgl(87) the bavg registers are the average intensity value for all blue pixels in the area defined by the roi registers. this register is updated at the end of the active pixels and before vertical blanking. the register always contains a valid value of the most re cent frame. 8.3.5 lumavgh(88) & lumavgl(89) the lumavg registers are the average intensity value for all pixels in the area defined by the roi registers. this register is updated at the end of the active pixels and before vertical blanking. the register always contains a valid value of the most re cent frame. 8.3.6 replpix(a0) the replpix register is a count of the number of pixels that have been replaced by the pixel replacement algorithm. if more than 255 pixels have been replaced, the value is clipped to 255. 8.3.7 currow(a1) the currow register contains the eight most-significant bits of the 11-bit row counter. thus, currow indicates where the imager is currently reading data from the image array. note that this value may jump quickly from one part of the image to the bit # name dir default function 15:0 gravg r green-red pixel value average bit # name dir default function 15:0 gbavg r green-blue pixel value average bit # name dir default function 15:0 ravg r red pixel value average bit # name dir default function 15:0 bavg r blue pixel value average bit # name dir default function 15:0 lumavg r pixel value average bit # name dir default function 7:0 replpix r number of pixels replaced bit # name dir default function 7:0 currow r eight msbs of the current row
cyiwosc3000a a document #: 38-19009 rev. *e page 31 of 37 other when sub-windowed. a value of zero indicates that a new frame has just started. a value above 196 indicates we are in vertical blanking. 8.3.8 noisevarh(a2) & noisevarl(a3) the noisevar register is a 16-bit register which holds the nois e variance of the current frame. the noise variance is the squar e of the difference of a pixel and the previous frames blklvl. the noise variance is accumulated for 214 pixels in the top dark rows. the noise variance is typically used to assist the image processing software in setting limits on gain to maintain a reasonable signal-to-noise ratio. 8.3.9 actrowsh(a4) & actrowsl(a5) the actrows register provides a count of the number of active rows per frame. the number of active rows per frame depends on the setting of many registers and may be difficult to compute. this register provides an easy way to determine the number of active rows per frame for the current operating mode. 8.3.10 actcolsh(a6) & actcolsl(a7) the actcols register provides a count of the number of active pixels per row. the number of active pixels per row depends on the setting of many registers and may be difficult to compute. this register provides an easy way to determine the number of active pixels per row for the current operating mode. 8.3.11 colcnt(a8) & colcnt(a9) the colcnt register is a read-only register that provides the num ber of clocks per row. it is a twelve bit register and hence i f more than 4096 clocks/row are progr ammed the register will reset to 0 and begin the next count. 8.3.12 tintaeh(aa) & tintael(ab) the tintae register is a read-only register that provides the current integration time when the autoexposure unit is enabled. the integration time typically changes every frame when the auto exposure unit is enabled. this register is updated just before the start of a new frame and is the value being used while the frame is being captured. bit # name dir default function 15:0 noisevar r variance of the noise in the top dark pixels. bit # name dir default function 11:0 actrows r number of active pixels per row bit # name dir default function 11:0 actcols r number of active pixels per column bit # name dir default function 11:0 colcount r number of clocks per row bit # name dir default function 11:0 tintae r integration time in rows when autoexposure is enabled
cyiwosc3000a a document #: 38-19009 rev. *e page 32 of 37 9.0 feature descriptions 9.1 hisens? this circuit provides reduced readout noise using circuitry both inside and peripheral to the imaging area. 9.2 power saver settings there are three power modes on the sensor to provide a balance of imager performance and power consumption, as described in table 9-1 . the imager default (power-up) setting is in power mode 1 but will inhibit output video until it has stabilized to avoid displaying bad frame data. significant power savings can be obtained by running the imager at a slower clock frequency, reducing the active pixel area (subwindowing) or by sub-sampling the image. this allows the imager to run in an active preview mode at substantially reduced power levels but return briefly to a high power mode when taking a full 3mp capture. 9.3 selectable frame rate frame rate can be adjusted by a number of factors. the clk frequency sets the basic frame rate and can be as high as 48 mhz. to readout a full 3mp image in 1/14th of a second requires a 48-mhz clk. the frame rate can also be adjusted by varying the number of vblank rows. the number of vblank rows can be up to 4095, allowing for a wide range of frame rates. subwindowing will also increase the frame rate as fewer rows need to be read out. note that binning does not increase the frame rate as the imager must still collect all of the pixels but the data rate out of the pixel data bus is significantly lower in these modes. windowing into a relatively small number of rows can increase the frame rate for high-speed auto-focus applications. reading out just the middle third of the image area will increase the frame rate by 3x. decreasing the number of columns does not change the frame rate as all pixels in a row must be read out to keep the row timing consistent. table 9-1. power modes mode video operation serial communication operation active (power mode 1) full functionality digital video output full functionality registers retain settings standby with exposure (power mode 2) imager maintains exposure no video is output read all registers write to power register only registers retain settings full standby (power mode 3) no imager operation no video is output read all registers write to power register only registers retain settings table 9-2. typical power consumption in common operating modes power mode operation analog and digital power consumption (v ddd = 1.8v, v dda = 2.8v) full frame full speed capture 2048 x 1536 14 fps with 48-mhz clk i dda = 59 ma i ddd = 27 ma p = 215 mw preview mode 640 x 480 30 fps with 18-mhz clk i dda = 15 ma i ddd = 9 ma p = 60 mw standby/idle mode reset low clk = 0 hz i dda = 1 a i ddd = 3 a p = 8 w
cyiwosc3000a a document #: 38-19009 rev. *e page 33 of 37 9.4 fpn reduction column fixed pattern noise reduction: the imager collects pattern data generated in the dark rows for fixed pattern noise and computes correction values to reduce this noise. a test voltage is applied to the adcs during 16 rows of vblank and the results are accumulated and stored in a special row buffer. this offset is then subtracted digitally. this subtraction is done to all pixels including the dark pixels. point defect correction: pixels operating outside of the response of their neighbors may be defective. the CYIWOSC3000AA imager will compare the response of the neighbor pixels and will replace the defective pixel with the nearest same color. all of these modes can be disabled via software. 9.5 black level setting and averaging the electronic and dark current induced offsets that cause black level errors will be removed on-chip. the imager will collect statistics on the electr onic black level from optically shielded pixels. these statistics will provide an average value for subtracting from active pixels. the first 8096 pixels in the top 12 dark rows are accumulated and an average is calcu- lated. the remaining pixels in the image have this value subtracted from them. this algorithm has the advantage of collecting statistics for the current frame and applying them immediately which will improve quality as it will track changes in tint. pixels that have the upper 4 msbs set are not included in the black level calculation. this insures that ?hot? pixels are ignored which might otherwise cause the average to be unusually high. there is a mask register that allows any of the 12 rows to be not used in the black level calculation. this allows certain rows to be excluded which are found to not be truly black. only four rows are typically needed for the black level calculation. 9.6 digital gain per color a 12x12 multiplier can be applied to each of the four color channels (r, gr, gb and b) individually via registers. the default is to multiply by 1 which has no effect. these multipliers provide digital gain typically used correct the responsivity of the color masks. if the color va lue exceeds 12 bits after the multiplication, then the color is saturated to the maximum value. the multiplication factor is in a 12-bit register with a 4.8 fixed point format. the value is rounded to the nearest by adding 128 to the result before shifting right by 8. 9.7 exposure control the imager provides for both automatic and manual control of the exposure or integration period. the exposure control algorithm sets the imager base integration period to set the average pixel value at a default or user specified level. in addition to setting the desired image average, the user may limit the integration period available to the automatic control. these registers may be used to prevent the integration from exceeding motion blur limits in dark environments. 9.8 resolution control the imager contains severa l blocks to control the output resolution and field of view (fov). by combining these blocks, many combinations of resolution/fov are available to the user via register setting. 9.9 sub-window control the imager can be read out at any sub-frame resolution on bayer boundaries (odd columns and even rows) down to 2h x 2v pixels. the blanking time minimums are required. the size of the sub-window is specified in the registers by setting the coordinates of the corners. the location of the sub-window can start at any bayer boundary. 9.10 analog on-chip binning binning can be performed in the analog domain to indepen- dently combine pixels in the horizontal and vertical dimensions with factors of 2, 3 (vertical only) and 4 adjacent bayer pixels. by combining pixels the low-light signal-to-noise ratio is increased. the imager architecture was tuned for on-chip binning factors of 2, 3, and 4. binning by 3 can only be done in the vertical dimension. analog binning has the advantage that it increases the frame rate. however, binning by more than 2x is not as flexible in analog as it is in digital. analog binning is also lower power than digital binning. generally, analog binning by 2 should be used whenever possible. 9.11 digital on-chip binning the imager provides addition al digital binning to support reduced resolution output modes. digital binning can be performed in both the horizontal and vertical dimensions. vertical binning is limited to 2x and 4x. horizontal binning can be any combination of 2, 3, or 4x in two stages. thus, horizontal binning can be 2, 3, 4, 6, 8, 9, 12, or 16x. there are two pixel weighting modes for digital binning. the weighting for each pixel can either be the normal 1:1 weighting, or a special mode where the appropriate color of the bayer pattern is weighted more favorably based on the location in the super-pixel. subsampling can be performed instead of binning, which increases the frame rate and lowers power consumption, however the image may tend to ?sparkle? due to aliasing artifacts. subsampling in the vertical dimension will increase the frame rate however subsampling in the horizontal dimension will not. it is recommended to subsample vertically wherever possible and always use binning in the horizontal dimension. 9.12 50-/60-hz flicker reduction flicker reduction involves setting the integration time to be a multiple of either 100 or 120 hz. this will insure that in relatively low-light situations where the lighting is likely to be from fluorescent bulbs, the image does not ?beat? with the flicker of the fluorescent bulbs. software must perform this function and properly set the integration time to be a multiple of 100 or 120 hz. 9.13 blanking time, pclk and sync polarity the polarity of the hsync, vsync, and pclk signals can be inverted by setting the proper register. additional hblank pixels and vblank rows can be added to the image frame by setting the appropriate registers.
cyiwosc3000a a document #: 38-19009 rev. *e page 34 of 37 9.14 power-on reset the CYIWOSC3000AA powers up automatically to default register mode operation as specified in this document. no serial communications are required on power-up to initiate image capture, the imager will output video imagery at full resolution with associated sync signals. the reset_n signal should be asserted until both power supplies have reached their proper voltage level and the clk is stable. 9.15 on-chip test pattern generation a test pattern will be output from the imager when set by the registers to provide a standard smpte color bar pattern. this is to assist with system development and testing. a represen- tation of the test pattern is shown in figure 9-1 with rgb values of 8-bit depth. the output of the test pattern will be in raw bayer form and each sample may be adjusted on chip using the digital gain per color channel registers. a configu- ration row of data may optionally be inserted into row 0 of the image. this configuration row contains data such as the frame number. tint value and other parameters. this mode is only used for testing and debug. 9.16 exposure control region of interest (roi) the camera includes a region of interest feature that can be used to influence the automatic control of the integration period. the region is defined by specifying the upper left and lower right corners of a rectangle using pixel row and column numbers. the exposure calculations can generated with pixels within the region or on those that lie outside the region. 9.17 register setting sync control most of the configuration registers have a shadow register that will hold the new value until the next vsync. this insures that all of the registers are updated at the same time and no bad frames are output. see the definition of the sync register for more details. 9.18 preview and video mode the imager generates a video signal at up to 14 fps (full frame) with internally generated clo cks and synchronization signals. these synchronization signals are output to other devices together with the processed image data. 9.19 parallel digital interface the CYIWOSC3000AA image sensor offers 8 and 12-bit parallel digital interfaces. this interface is configured to operate in a variety of modes to maximize compatibility with a variety of dsp interfaces and other custom applications. the imager samples and processes 12-bit data. if an 8-bit output is selected, the 12-bit data is mapped to 8-bit either with a fixed non-linear curve or linear mapping. the parallel digital output option will have the following output modes: 1. 12-bit data out, with hsync, vsync, pclk 2. 8-bit data out with hsync, vsync, pclk 3. each of the previously mentioned modes with embedded sync. the hsync and vsync are embedded by substitut- ing raw pixel values of assigned sync levels. this will allow client devices to sync up to the timing codes in the data stream. figure 9-1. smpte color bars
cyiwosc3000a a document #: 38-19009 rev. *e page 35 of 37 10.0 electrical specifications 10.1 absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature: ................................... .?30c to 85c input voltage: ......................................... ?0.2v to v cc +0.2v esd susceptibility (hbm): ..........................................2000v 10.2 operating conditions supply voltage: ........................................... 2.8 and 1.8vdc operating temperature: ............................... ?30c to +70c 11.0 electrical characteristics the following specifications apply for t a = 25c environmental specifications table 11-1. environmental specifications electrical characteristics parameter description conditions min. typ. max. unit vdd digital supply voltage 1.65 1.8 2.0 v vaa analog supply voltage 2.5 2.8 3.1 v p analog and digital power consumption @ 30 fps (640 x 480) 60 mw @ 14 fps (2048 x1536) 215 mw digital i/o v oh28 output level [high] i oh = ?4.0 ma vaa ? 0.2 v v ol28 output level [low] i ol = 4.0 ma 0.2 v v oh18 output level [high] vdd ? 0.2 v v ol18 output level [low] 0.2 v v ih28 input level [high] vaa ? 0.3 vaa + 0.3 v v il28 input level [low] ?0.3 0.3 v v ih18 input level [high] vdd ? 0.3 vdd + 0.3 v v il18 input level [low] ?0.3 0.3 v i load input leakage current v i = 0v to 3.0v 10 a c in input capacitance v in = 0v, f = 1.0 mhz 10 pf c out output capacitance v in = 0v, f = 1.0 mhz 12 pf pclk max pixel output rate 48 mhz specification value comment operating junction temperature ?30c to +70c see performance specifications for sensitivity de-rating over temperature storage temperature ?30c to 85c junction dust 100 mg/m 3-
CYIWOSC3000AA document #: 38-19009 rev. *e page 36 of 37 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. 12.0 48-pin plcc package diagram 12.1 ordering information purchase of i 2 c components from cypress or one of its sublicensed as sociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided t hat the system c onforms to the i 2 c standard specification as defined by philips. hisens is a trademark of cypress semic onductor corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. dimensions in millimeters reference jedec : na package weight : tbd part # table qp48a qy48a windowed plastic leadless chip carrier (standard) windowed plastic leadless chip carrier (lead free) glass lid 14.22 sq. 13.00 sq. 0.500.05 1.00 2.100.10 0.500.125 0.500.05 13.20sq.0.05 1.56 1.010.05typ 0.50typ. r0.400.05 1.00 2.00 ?0.400.05typ. c0.20 bottom view top view side view 001-00453-** figure 12-1. 48-pin plcc package diagram table 12-1. ordering information ordering code package name package type CYIWOSC3000AA - qyc qy48a 48-pin plcc package
cyiwosc3000a a document #: 38-19009 rev. *e page 37 of 37 document history page document title: CYIWOSC3000AA 3.1 megapixel cmos sensor document number: 38-19009 rev. ecn no. issue date orig. of change description of change ** 355657 see ecn hbh new data sheet *a 384066 see ecn hbh added detail to meet final product specifications *b 414413 see ecn syt converted from preliminary to final changed optical format from 1.3? to 1.28 ? removed 10-bit parallel data port information added analog and digital power consumption specs changed the true output dynamic range from 72 db to 60 db removed the snr max for xga and qvga resolutions changed the snr max spec from 42 to 39 and 51.5 to 43 for the qxga and the vga resolutions respectively. changed analog supply voltage from 2.65v - 3.1v to 2.5v - 3.1v i 2 c made consistent in the whole of the document corrected typo in the rownumh/rownuml and colnumh/columnl descrip- tions on page #: 14 and 15 appended information for reset(7e) register description on page# 27 edited the colcnt register descriptions on page # 30 changed the contents of table 8.2 changed vaa min from 2.52 to 2.5 v in table #9.1 included ?frames per second and integration time calculation? section. removed salt mist atmosphere, chemical resistance and humidity specifications from table # 10.0 *c 416566 see ecn syt changed address of cypress semi conductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? changed the max data rate/master clock rate from 100 mps/100 mhz to 48 mps/48 mhz changed frame rate from 30 fps to 14 fps for 2048 x 1536 mode and from 83 fps to 80 fps for 640 x 480 mode. changed the dynamic range from 55 db to 60 db included unit for snr max changed snr max from 39 to 35 db for qxga and from 43 to 40 db for vga changed the analog and digital power consumption spec from 55mw @ 30 fps (640 x 480) to 60 mw and 195 mw @ 15 fps (2048x1536) to 215 mw @ 14 fps. changed the clock frequency for preview mode from 12mhz to 18 mhz on table 8-2 on page # 31 *d 431055 see ecn syt added 48-plcc package diagram *e 436607 see ecn qgs updated bond diagram for 48-plcc package on page # 5. added note on page # 5. changed time required to read out a sing le row to colcnt / clk freq from clk freq / colcnt on page # 10. added hblank register number (0x8, 0x9) on page 10.

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